3월30일(목) 대학원세미나 Prof. Jeong Ho Cho(SKKU Advanced Institute of Nanotechnology (SAINT), School of Chemical Engineering, Sungkyunkwan University, Suwon, Korea)
|초청강사||Prof. Jeong Ho Cho|
|소속||SKKU Advanced Institute of Nanotechnology (SAINT), School of Chemical Engineering, Sungkyunkwan University, Suwon, Korea|
|일시||2017년 3월 30일(목) 오후5시|
We demonstrate a new device architecture for flexible vertical Schottky barrier (SB) transistors and logic gates based on graphene–organic semiconductor–metal heterostructures and ion gel gate dielectrics. The vertical SB transistor structure was formed by (i) vertically sandwiching a benchmark p-type pentacene or n-type N,N’-dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C8) organic semiconductor layer between graphene (source) and metal (drain) electrodes and (ii) employing a separate coplanar gate electrode bridged with the vertical channel through an ion gel. The channel current was modulated by tuning the Schottky barrier height across the graphene–organic semiconductor junction under an applied external gate bias. The high specific capacitance of the ion gel gate dielectrics enabled the work function of the graphene to be readily modulated using a voltage below 1 V. Consequently, the devices showed well-behaved p- and n-type characteristics under low-voltage operation (< 1 V), yielding high current densities (> 100 mAcm–2) and on–off current ratios (> 103). The simple structure of the unit transistor enabled successful fabrication of low-power logic gates based on assemblies of devices such as the complementary inverter, NAND, and NOR circuits on a plastic substrate. The simple, scalable, and room-temperature deposition of both organic semiconductors and gate dielectrics integrated with transparent and flexible graphene opens up new opportunities for realizing future transparent, flexible, and low-power organic electronics.
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